This series from Teledyne LeCroy is designed to take you from the fundamentals of DDR memory testing to advanced DDR PHY compliance, validation, and debug techniques. Across four sessions, you’ll learn how to improve DDR validation efficiency, troubleshoot common challenges, and understand the latest DDR5 test requirements, including eye diagram and jitter measurements.
Part 3: DDR Debug and Virtual Probing
Date: Wednesday October 7, 2026
Time: 11:00AM Pacific | 2:00PM Eastern
Duration: 60 minutes
In this webinar, we provide practical advice on overcoming DDR test challenges using debug tools. Topics include real-world DDR debugging examples like logic, soldering, and power supply issues, DDR read/write separation, eye pattern formation, and addressing missing clock cycles. We’ll also discuss DDR eye patterns, jitter in multiple scenarios, hardware-based read-write separation, and virtual probing techniques.
Presenter: Mike Hertz, Senior Field Applications Engineer
Can’t attend live? Register anyway and you will receive an email with the recording and slides after the live event.