This series from Teledyne LeCroy is designed to take you from the fundamentals of DDR memory testing to advanced DDR PHY compliance, validation, and debug techniques. Across four sessions, you’ll learn how to improve DDR validation efficiency, troubleshoot common challenges, and understand the latest DDR5 test requirements, including eye diagram and jitter measurements.
Part 2: Tips and Techniques for DDR Probing
Date: Wednesday September 30, 2026
Time: 11:00AM Pacific | 2:00PM Eastern
Duration: 60 minutes
In this webinar, we get specific on how to address real-world probing and connectivity issues that impact DDR measurement capabilities. We will provide examples of what to do or not do and a pre-compliance test checklist will be reviewed.
Presenter: Mike Hertz, Senior Field Applications Engineer
Can’t attend live? Register anyway and you will receive an email with the recording and slides after the live event.