1/28/2020-1/30-2020 – Join Anritsu at DesignCon


Anritsu’s Hiroshi Goto to participate in Panel—The Case of the Closing Eyes: PAM is the Answer, or Not?

Tuesday, January 28, 4:45 PM – 6:00 PM, Ballroom F Add to Calendar

Join this panel of experts for a lively discussion on the state of testing practices for high-speed networking technologies. This year's panel will be evaluating the pros and cons of characterization efforts for 400GbE over PAM4. Chip experts will discuss design verification challenges while the test & measurement industry veterans will provide direction on testing implementation plans. Come prepared to engage in the discussion!

See Anritsu’s latest signal integrity products at Booth 837

Anritsu will showcase its leading test solutions and techniques to verify high-speed communications featuring the latest technologies, including PCI Express® (PCIe®) 3.0/4.0/5.0 and Ethernet PAM4, during DesignCon 2020 in booth #837. Test solution demonstrations will include:

  • 400G Optical PAM4 TDECQ Test
  • 400G JTOL Test for PAM4 with FEC
  • PCIe G4/G5 LEQ RX Compliance Test
  • Automated High Speed Serial Bus RX Test
  • De-embedding with Universal Fixture Extraction
  • 110 GHz Signal Integrity Measurement

Attend Anritsu's technical sessions and register for a chance to win an Echo Show & Ring!

Thursday, January 30, Great America – Room 2 - Add to Calendar

Request a meeting! CLICK HERE