06/16/2021 How to De-embed Interconnect Elements in Both Frequency and Time Domains

How to De-embed Interconnect Elements in Both Frequency and Time Domains

Date: Wed, June 16, 2021
Time: 11AM Pacific | 2PM Eastern
Duration: 60 minutes

REGISTER HERE

Join Teledyne LeCroy as we describe and demonstrate best practices for de-embedding test fixtures, cables, and probes from serial data link and other signal integrity measurements. This is a critically important process to ensure that the signal integrity measurements for the DUT are not contaminated by the interconnection elements.

Topics to be covered in this webinar:

  • Why de-embedding is almost always necessary
  • Best practices for reference-plane calibration
  • Traditional Frequency-domain de-embedding
  • Time-domain gating and peeling (i.e. fixture removal, in-situ de-embedding (ISD))
  • Causality conditions

Who should attend? Hardware engineers who use a Vector Network Analyzer (VNA) to obtain S-parameters for use in emulation software.

What attendees will learn?  How to accurately measure S-parameters of high-speed interconnects.

Presenter: Giuseppe Leccia, Business Development Manager

Can’t attend live? Register anyway, and we will send you the recording and slides afterward.